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IDT71V3577S_79S, IDT71V3577SA_79SA, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Pin Definitions (1)
Symbol
A 0 -A 17
Pin Function
Address Inputs
I/O
I
Active
N/A
Description
Synchronous Address inputs. The address register is triggered by a combi-nation of the rising edge of CLK
and ADSC Low or ADSP Low and CE Low.
ADSC
Address Status
I
LOW
Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is used to load the
(Cache Controller)
address registers with new addresses.
ADSP
Address Status
I
LOW
Synchronous Address Status from Processor. ADSP is an active LOW input that is used to load the address
(Processor)
registers with new addresses. ADSP is gated by CE .
ADV
Burst Address
I
LOW
Synchronous Address Advance. ADV is an active LOW input that is used to advance the internal burst counter,
Advance
controlling burst access after the initial address is loaded. When the input is HIGH the burst counter is not
incremented; that is, there is no address advance.
BWE
Byte Write Enable
I
LOW
Synchronous byte write enable gates the byte write inputs BW 1 - BW 4 . If BWE is LOW at the rising edge of CLK
then BW x inputs are passed to the next stage in the circuit. If BWE is HIGH then the byte write inputs are
blocked and only GW can initiate a write cycle.
BW 1 - BW 4
Individual Byte
I
LOW
Synchronous byte write enables. BW 1 controls I/O 0-7 , I/O P1 , BW 2 controls I/O 8-15 , I/O P2 , etc. Any active byte
Write Enables
write causes all outputs to be disabled.
CE
CLK
CS 0
CS 1
GW
Chip Enable
Clock
Chip Select 0
Chip Select 1
Global Write
I
I
I
I
I
LOW
N/A
HIGH
LOW
LOW
Synchronous chip enable. CE is used with CS 0 and CS 1 to enable the IDT71V3577/79. CE also gates ADSP .
This is the clock input. All timing references for the device are made with respect to this input.
Synchronous active HIGH chip select. CS 0 is used with CE and CS 1 to enable the chip.
Synchronous active LOW chip select. CS 1 is used with CE and CS 0 to enable the chip.
Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on the rising edge of
Enable
CLK. GW supersedes individual byte write enables.
I/O 0 -I/O 31
Data Input/Output
I/O
N/A
Synchronous data inp ut/output (I/O) pins. The data input path is registered, triggered by the rising edge of
I/O P1 -I/O P4
CLK. The data o utput path is flow-through (no output register).
LBO
Linear Burst Order
I
LOW
Asynchronous b urst order selection input. When LBO is HIGH, the inter-leaved burst sequence is selected.
When LBO is LOW the Linear burst sequence is selected. LBO is a static input and must not change state
while the device is operating.
OE
Output Enable
I
LOW
Asynchronous output enable. When OE is LOW the data output drivers are enabled on the I/O pins if the chip
is also selected. When OE is HIGH the I/O pins are in a high-impedance state.
TMS
TDI
TCK
TDO
TRST
Test ModeSelect
Test Data Input
Test Clock
Test DataOutput
JTAG Reset
(Optional)
I
I
I
O
I
N/A
N/A
N/A
N/A
LOW
Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an
internal pullup.
Clock input of TAP co ntroller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK,
while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.
Serial output of registers placed be tween TDI and TDO. This output is active depending on the state of the
TAP controller.
Optional Asynchronous JTAG rese t. Can be used to reset the TAP contro ller, but not required. JTAG reset
occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST can
be left floating. This pin has an internal pullup. Only available in BGA package.
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V3577/79 to
ZZ
Sleep Mode
I
HIGH
its lowest power consumption level. Data retention is guaranteed in Sleep Mode.This pin has an internal pull
down.
V DD
V DDQ
V SS
NC
Power Supply
Power Supply
Ground
No Connect
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3.3V core power supply.
3.3V I/O Supply.
Ground.
NC pins are not electrically connected to the device.
6450 tbl 02
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
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